#HiringFPGA Design EngineerExp-5- 8YearsNotice Period- 0 to 15DaysLocation- Bangalore Job Description: <ul><li>RTL and FPGA design, implementation, and timing closure using Xilinx &amp; Synopsys development tools.</li><li>Bring up and validate the design in the lab and generate test reports.</li><li>Perform hardware validation tasks and debug IPs.</li><li>Read, understand, and modify software drivers and scripts.</li></ul> Skills <ul><li>RTL Design &amp; FPGA Implementation: Verilog, System Verilog, Vivado , ISE, Synplify, Design Compiler</li><li>FPGA Platforms: Xilinx 7-series, Ultrascale/Ultrascale+, Zynq</li><li>Toolchain Expertise: Xilinx Vivado, Synopsys DC/PT, ModelSim, VCS</li><li>Hardware Validation: Bitstream generation, on-board debugging, performance tuning</li><li>Lab Equipment: Oscilloscopes, logic/protocol analyzers, JTAG debuggers</li><li>Software &amp; Scripting: C, C++, Python, Perl, TCL, Bash</li><li>Operating Systems: Linux (device driver understanding), embedded systems</li></ul> Interested candidates share your resume to sreeja.s@sasnee.com