Job Title: Memory Layout Engineer Location: Bangalore Job Type: Full-Time Experience: 4-10 Years Educational Qualification: <ul><li>Bachelor’s degree in Electrical or Electronics Engineering or equivalent Key Responsibilities</li><li>Design and development of critical memory layouts and provide integration support</li><li>Perform layout verification including LVS, DRC, EM checks, quality checks, and documentation</li><li>Deliver block-level and top-level layouts on time with acceptable quality standards</li><li>Plan, estimate area/time, schedule, delegate, and execute tasks to meet project milestones</li><li>Collaborate with cross-functional teams across multiple projects</li><li>Manage and resolve technical roadblocks and escalations to ensure timely delivery</li><li>Provide alternative technical solutions to clients where required</li><li>Build team capability to maintain operational excellence and customer service levels</li><li>Communicate effectively with engineering teams across different geographical locations</li></ul> Required Skills &amp; Experience: <ul><li>Industry experience in memory leafcell layout design</li><li>Strong understanding of memory architectures and performance optimization</li><li>Strong knowledge of FinFET technology</li><li>Hands-on experience in memory domain including characterization, design, and validation</li><li>Proficiency in writing SPICE decks, stimulus, and test vectors</li><li>Experience with fast simulation tools and waveform viewers</li><li>Knowledge of layout parasitic extraction and deep submicron technology challenges</li><li>Strong LVS/DRC debugging skills and verification for lower technology nodes</li><li>Familiarity with EDA tools including Cadence SKILL scripting and automation for compiler flows and layout reuse</li><li>Familiarity with NMDL and CCST libraries</li><li>Experience in generating libraries and performing QA sign-off</li><li>Understanding of layout impact on speed, capacitance, power, and area</li><li>Ability to understand design constraints and implement high-quality layouts</li><li>Good problem-solving, critical thinking, and interpersonal skills</li></ul>

Memory Layout Engineer

Job Title: Physical Design EngineerJob Type: Onsite Location: Bengaluru Experience: 4+ Years Responsibilities: <ul><li>Handle end-to-end physical design: floor planning, placement, CTS, routing, and signoff</li><li>Drive timing closure and optimize PPA (power, performance, area)</li><li>Fix setup/hold violations using STA</li><li>Ensure DRC/LVS and IR/EM clean design</li><li>Work closely with RTL, DFT, and verification teams</li></ul> Requirements: <ul><li>4+ years in ASIC/VLSI Physical Design</li><li>Hands-on with Cadence Innovus / Synopsys ICC2</li><li>Strong in STA using Synopsys PrimeTime</li><li>Knowledge of physical verification using Mentor Calibre</li><li>Scripting in TCL/Shell/Python</li></ul>

Physical Design Engineer

Job Title: Device Driver Validation EngineerLocation: BengaluruExperience Required: 3–7 YearsEmployment Type: Full-Time Job Description -We are looking for Device Driver Validation Engineers with hands-on experience in Linux multimedia video and camera drivers based on the V4L2 framework. The role involves testing, debugging, and analyzing driver-level issues using logs and tools. Key Responsibilities -Testing video drivers on Linux (mandatory), Android OS, and Chrome OSExecute test cases using Python test frameworkDebug and triage issues based on log analysisIdentify issues in code through log file analysisInterface with developers for issue resolution Skills &amp; Requirements -Hands-on experience in Linux multimedia video and camera drivers (V4L2 framework)Strong understanding of log analysis and debugging toolsFamiliarity with:dmesg, journalctl/dev, /sys, /procKernel logs, stack traces, call traces

Memory Layout Engineer Jobs in Bengaluru

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